[BrianG]

The second link requires login to see any schematics, but it just talks about paralleling bipolar transistors. You have to be very careful with regular transistors because as they heat up, they conduct more. This leads to "current hogging" and the best transistor of the parallel array (best meaning highest current gain and lowest C-E saturation voltage) will hog most of the load and burn out. Then, the next best transistor will do the same, and so on until they all burn out. There are ways to safeguard against this (using small value, but large power resistors on the emitter), but it is a PITA IMO. Not to mention the voltage drop on these resistors creates heat and power loss (lower efficiency) and means you need a higher input voltage than normal to ensure it stays high enough above the desired output for proper operation (also known as drop out voltage). Much easier to parallel FETs because they conduct less as they heat up, which results in a sort of "self-regulation".

The second page is probably closer to what I am looking for, but some important diagrams are missing.

Thanks for the effort though. I guess I will either keep searching, or use a bazillion PNP pass transistors in parallel with emitter resistors. Ugg.